Joseph F. Baker

SUMMARY:
. Senior engineer experienced in the design of embedded hardware and firmware.
. Driven to achieve project success enabling others to meet their goals.

EXPERTISE:
. Embedded Controller Design . . . . . Digital, Mixed Signal and A/D
. Microprocessor based design . . . . .DC to DC point-of-load power
. Video, Telecom & Datacom . . . . . . Orcad & Altium Schematic Capture
. Real-time, multi-tasking c Firmware .Microchip, Atmel, Freescale & NXP

PROFESSIONAL HISTORY:
RLA Engineering Portland, OR . . . . . .2014 – Now
• Engineering lead / hardware design of a Bluetooth personal emergency device.
. . Intel Curie SoC with Dual Path power and a separate Battery Charger
. . Managed layout, purchasing and assembly of electronics & custom enclosure
. . Recruited and mentored junior SW engineer to develop the application
. . Technical interface to customers, contract manufacturing and other vendors
• Hardware & firmware design of a kAmp-hr sensor retrofit of plating tanks
• FW & digital HW design for a beverage maker in a dual PIC MX795 architecture

Radio System Engineering Consulting . . Portland, OR 2008 – 2013
• Designed after-market HW mods to increase radio power & frequency performance
• Designed microwave & mobile radio systems using EDX, ComStudy and Pathloss
.
Family Leave Coos Bay, OR 2006 – 2007
I paused my career for my (former) spouse’ teaching career in Coastal/Central Oregon
.
Rosen Aviation Displays . . . . . . . . Eugene, OR 2005 – 2006
( In-cabin displays for entertainment on private aircraft )
. . Root cause identification of failure modes and reliability concerns
. . Provided insight and assistance resolving production issues
.
Georgia Department of Education Atlanta, GA 2003 – 2004
. . Certified High School Math Teacher – Class of 2003 ‘s “Most Dedicated Teacher”
.
Intelligent Optical Amplifiers . . . . . San Jose, CA 2001 – 2002
. . Designed embedded MPC855T and MPC8260 with SDRAM, FLASH, DSP
. . Verilog RTL in Altera FPGA’s distributed logic of 19 bit multiply and signed addition
. . All layout, purchasing and manufacturing support for prototype assembly and test

VINA Technologies . . . . . . . . . . . .San Jose, CA 1998 – 2001
. . Designed Freescale MPC860 based hardware for a voice/data E1 aggregator
. . Designed Freescale MPC8260 based hardware with FLASH, SDRAM, and L2-Cache
. . Altera & Xilinx CPLDs for Bus Arbitration, Null Pointer Detection and Chip Selects
.
Previously . . . . . . . . . . . . . . . Atlanta, GA 1990 – 1998
. HW design of very high volume home analog & digital TV receiver product lines:
. . Resolved clock jitter bug by designing a transport stream buffer in Altera RTL Verilog
. . Video digital to analog conversion & timing for multiple international video formats
. . Designed one NXP 8051 firmware and hardware to drive multiple front panel UIs:
. . HW & FW design of a PIC18-based replacement for I2C LCD during production
. . Design of a PLD to replace a timing IC that had been discontinued during production
. . LNA power supply with variable output, modulated & active short-circuit protection
. . Designed In-Circuit-Emulator for secure microcontroller that had not taped-out
. . Created necessary production documentation for efficient HVM handoff.
.
EDUCATION:
Georgia Institute of Technology . . . . . BSEE
East Tennessee State University . . . . . BA in Music Education

  • Updated 5 years ago

To contact this candidate email joe@joseph-baker.com

Contact using webmail: Gmail / AOL / Yahoo / Outlook

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